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Google's 'Frozen V2' TPU hardwires SRAM onto silicon, ditching TSMC's CoWoS packaging for Gemini
In the ongoing AI competition, Google introduces its 'Frozen V2' TPU, which embeds SRAM onto silicon, bypassing TSMC's CoWoS technology. This shift is designed to optimize performance for its Gemini AI models, enhancing efficiency and potentially streamlining production processes. The strategic move reflects a broader trend in tech towards customized chip designs that prioritize direct integration for better performance in AI applications.
MonitorConfidence: MediumShort term horizon
Published 27 Jul 2026, 18:20 UTC2 min read
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Summary
TL;DR
- Google's TPU chips focus on AI capabilities.
- The 'Frozen V2' chip eliminates TSMC's CoWoS packaging.
- Integration of SRAM directly onto silicon enhances chip performance.
- Early-stage production is planned for next year.
- This approach aims to reduce manufacturing dependencies.
Interesting facts
- Using hardwired SRAM addresses memory-compute bottlenecks.
- Similar methods have previously been employed by other AI chipmakers.
- Each new AI model may require a new chip design, complicating production.