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TSMC Concedes Intel's EMIB Packaging Is A Potent Contender, Starts Building "Quasi-EMIB" As CoWoS Remains Choked Through 2026
TSMC has recognized the need to adapt in the face of Intel's successful EMIB packaging, which offers advantages over TSMC's current CoWoS technology. With demand for TSMC's high-performance packaging outpacing supply and lead times extending significantly, the company aims to implement elements from Intel's design to enhance its offerings. The potential shift towards a quasi-EMIB solution signals TSMC's commitment to retaining its competitive edge in the semiconductor market as it faces increasing competition from Intel.
MonitorConfidence: MediumMid term horizonSupply chain risk: High
Published 30 Jul 2026, 16:20 UTC4 min read
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Summary
TL;DR
- TSMC's CoWoS capacity is constrained until 2026.
- Intel's EMIB technology is attracting significant orders.
- TSMC plans to build a quasi-EMIB packaging solution.
- The revised packaging aims to enhance efficiency in chip connectivity.
- EMIB technology eliminates the need for large silicon layers.
Interesting facts
- EMIB connects chips directly through embedded silicon bridges.
- TSMC's CoWoS-L utilizes separate intermediate layers for chip connectivity.
- Lead times for TSMC's products have reportedly stretched to 78 weeks.