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ProPakistani
TSMC’s New Tech Could Improve Performance and Cut AI Chip Costs
TSMC has announced it is developing a new advanced chip packaging technology named CoPoS, which aims to enhance the performance of AI chips while simultaneously cutting costs. CoPoS, or Chip-on-Panel-on-Substrate, utilizes a novel panel-level packaging method instead of the traditional wafer-based approach, which is expected to enter mass production by 2028. This development is particularly significant as AI chips scale up in size and complexity.
MonitorConfidence: HighMid term horizon
Published 12 Jun 2026, 07:59 UTC2 min read
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Summary
TL;DR
- TSMC's CoPoS technology focuses on panel-level packaging.
- Expected to enter mass production between 2028 and 2029.
- The method could reduce manufacturing costs for AI chips.
- Initial uses may involve Nvidia's upcoming Feynman AI chip.
- Panel-level process replaces traditional silicon wafers with glass substrates.
Interesting facts
- CoPoS is designed for ultra-large packages beyond 9.5x reticle-size.
- Glass is used temporarily during assembling chip components.
- TSMC's pilot line for CoPoS technology began tool installation in February.